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wt21 data sheet wednesday, 10 march 2010 version 1.74
bluegiga technologies oy copyright ? 2000 - 2010 bluegiga technologies all rights reserved. bluegiga technologies assumes no responsibility for any errors which may appear in this manual. furthermore, bluegiga technolo gies reserves the right to alter the hardware, software, and/or specifications detailed here at any time without notice and does not make any commitment to update the information contained here. bluegigas products are not authorized for use as critical co mponents in life support devices or systems. the wrap is a registered trademark of bluegiga technologies the bluetooth trademark is owned by the bluetooth sig inc., usa and is licensed to bluegiga technologies. all other trademarks listed herein are owned by their respective owners.
bluegiga technologies oy version history version comment 0.1 first draft 0.2 block diagram, descriptions added 0.3 preliminary version 0.4 fixed ordering codes added captions 0.5 power control and regulation info added. layout guide updated. minor updates and fixes. 1.0 electrical characteristic added. some minor updates. 1.1 function of the regulator enable pin corrected. some minor updates. 1.2 new template 1.3 pinout fixed ( gnd pins 1 C 3 removed , pin 23 grounded ). layout guide updated. 1. 4 improved dimensions chapter 1.41 table 5 fixed (pad types) 1.5 footprint added 1.6 footprint fixed. pin number 3 (nc) added. 1.7 recommended pcb land pattern for wt21 - n added, power control and regulation updated. certification information added 1. 71 information about qualified antenna types added 1.72 minor updates to chapter 14.5 1.73 physical dimensions corrected 1.74 uart directions clarified to table 5
bluegiga technologies oy table of contents 1 ordering i nformation ................................ ................................ ................................ . 8 2 pinout and terminal description ................................ ................................ .................. 9 3 microcontroller, memory and baseband logic ................................ .............................. 12 3.1 auristream codec ................................ ................................ ............................. 12 3.1.1 auristream codec requirements ................................ ................................ ... 13 3.1.2 auristream hierarchy ................................ ................................ .................... 13 3.2 memory managements unit ................................ ................................ ................. 14 3.3 burst mode controller ................................ ................................ ......................... 14 3.4 ph ysical layer hardware engine dsp ................................ ................................ .... 14 3.5 wlan coexistence ................................ ................................ ............................. 15 3.6 configurable i/o parallel ports ................................ ................................ ............. 15 4 clock generation ................................ ................................ ................................ ..... 16 4.1 32khz external reference clock ................................ ................................ ........... 16 5 serial peripheral interface (sp i) ................................ ................................ ................ 17 5.1 wt21 serial peripheral interface (spi) ................................ ................................ .. 17 5.2 instruction cycle ................................ ................................ ................................ 17 5.2.1 writing to the device ................................ ................................ .................... 17 5.2.2 reading from the device ................................ ................................ ............... 18 5.2.3 multi - slave operation ................................ ................................ .................... 18 6 host interfaces ................................ ................................ ................................ ........ 19 6.1 host selection ................................ ................................ ................................ ... 19 6.2 uart interface ................................ ................................ ................................ .. 19 6.2.1 uart configuration while reset is active ................................ ........................ 21 7 csr serial peripheral interface (cspi) ................................ ................................ ........ 22 7.1.1 cspi read/write cycles ................................ ................................ ................. 22 7.1.2 cspi register write cycle ................................ ................................ .............. 23 7.1.3 cspi register read cycle ................................ ................................ .............. 23 7.1.4 cspi register burst write cycle ................................ ................................ ...... 23 7.1.5 cspi register read cycle ................................ ................................ .............. 24 7.2 s dio interface ................................ ................................ ................................ .. 25 7.2.1 sdio/cspi deep - sleep control schemes ................................ ......................... 25 7.2.2 retransmission ................................ ................................ ............................. 25 7.2.3 signaling ................................ ................................ ................................ ..... 25 8 audio interfaces ................................ ................................ ................................ ...... 26 8.1 pcm interface ................................ ................................ ................................ .... 26 8.1.1 pcm interface master/slave ................................ ................................ ........... 26
bluegiga technologies oy 8.1.2 long frame sync ................................ ................................ .......................... 27 8.1.3 short frame sync ................................ ................................ ......................... 28 8.1.4 multi - slot operation ................................ ................................ ...................... 28 8.1.5 gci interface ................................ ................................ ............................... 29 8.1.6 slots and sample formats ................................ ................................ ............. 29 8.1.7 additional features ................................ ................................ ....................... 30 8.1.8 pcm timing information ................................ ................................ ................ 31 8.1.9 pcm_clk and pcm_sync generation ................................ .............................. 34 8.1.10 pcm configuration ................................ ................................ ..................... 34 8.2 digital audio interface (i2s) ................................ ................................ ................ 37 9 power control and regulation ................................ ................................ .................... 40 9.1 power control and regulation ................................ ................................ .............. 40 9.2 vreg_enable ................................ ................................ ................................ ... 40 9.3 rst# ................................ ................................ ................................ ................ 40 9.4 digital pin states on reset ................................ ................................ .................. 41 10 bluetooth r adio ................................ ................................ ................................ .... 43 10.1 bluetooth receiver ................................ ................................ ........................ 43 10.1.1 rssi analogue to digital converter ................................ .............................. 43 10.2 bluetooth transmitter ................................ ................................ ................... 43 11 electrical characteristics ................................ ................................ ........................ 44 11.1 absolute maximum ratings ................................ ................................ ............ 44 11.2 recommended operating conditions ................................ ............................... 44 11.3 input/output terminal characteristics ................................ ............................. 44 11.3.1 linear voltage regulator ................................ ................................ ............. 44 11.3.2 digital ................................ ................................ ................................ ...... 45 11.3.3 reset ................................ ................................ ................................ ....... 45 11.3.4 32 khz external reference clock ................................ ................................ .. 45 11.4 power consumption ................................ ................................ ...................... 46 12 physical dimensions ................................ ................................ .............................. 47 13 layout guidelines ................................ ................................ ................................ . 50 13.1 wt21 - n ................................ ................................ ................................ ....... 50 13.2 wt21 - a ................................ ................................ ................................ ....... 50 14 certifications ................................ ................................ ................................ ........ 52 14.1 bluetooth ................................ ................................ ................................ .... 52 14.2 fcc ................................ ................................ ................................ ............ 52 14.3 ce ................................ ................................ ................................ .............. 53 14.4 industry canada (ic) ................................ ................................ .................... 53
bluegiga technologies oy 14.5 qualified antenna types for wt21 - n ................................ ............................... 53 15 contact information ................................ ................................ .............................. 54
bluegiga technologies oy wt21 bluetooth? hci module description wt21 is intended for bluetooth applications where a host processor is capable of running the bluetooth softw are stack. wt21 only implements the low level bluetooth host controller interface (hci) but still offers advantages of a module - easy implementation and certifications. applications: ? pcs and laptops ? pdas ? embedded systems features: ? fully qualified bluetooth v2.1 + edr system ? piconet and scatternet support ? low power consumption ? 1,8v to 3,6v i/o voltage ? integrated 1,8v regulator ? uart to 4 mbaud ? sdio (bluetooth type a) and cspi host interfaces ? deep - sleep sdio operation ? support for 802.11 coexistence ? r ohs compliant ? auristream baseband codec
bluegiga technologie s oy page 8 of 54 1 ordering information wt21 - a - hci product series fimrware hci = hci firmware hw version a = chip antenna, extended temperature range n = rf pin, extended temperature range
bluegiga technologie s oy page 9 of 54 2 pinout and terminal description figure 1 : wt21 pin out table 1 : terminal desc riptions 1v8_out vregin vreg_ena pio1 gnd gnd gnd gnd gnd gnd gnd gnd pio2 pio3 pio4 pio5 pio7 pio9 gnd 32khz uart_tx uart_rts# uart_rx gnd gnd uart_cts# sdio_clk sdio_sd_cs# sdio_cmd vdd_pads pcm_sync pcm_clk pcm_out pcm_in spi_miso spi_clk spi_cs# spi_mosi rst# gnd gnd gnd gnd gnd gnd gnd gnd rftp 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 3 nc pin number pad type description nc 3 not in use leave floating or connect to gnd rst# 42 input, weak internal pull- up active low reset. keep low for >5 ms to cause a reset gnd 23 gnd gnd
bluegiga technologie s oy page 10 of 54 table 2 : terminal descriptions table 3 : terminal descriptions power supplies pin number description vregin 12 input for the internal 1,8v regulator 1v8_out 11 1,8v regulator output vreg_ena 13 take high to enable internal voltage regulators gnd 4-10, 15-16, 28, 43-50 ground vdd_pads 33 positive supply for the digital interfaces pio port pin number pad type description pio[1] 14 bi-directional, programmamble strength internal pull-down/pull-up programmamble input/output line pio[2] 17 bi-directional, programmamble strength internal pull-down/pull-up programmamble input/output line pio[3] 18 bi-directional, programmamble strength internal pull-down/pull-up programmamble input/output line pio[4] 19 bi-directional, programmamble strength internal pull-down/pull-up programmamble input/output line pio[5] 20 bi-directional, programmamble strength internal pull-down/pull-up programmamble input/output line pio[7] 21 bi-directional, programmamble strength internal pull-down/pull-up programmamble input/output line pio[9] 22 bi-directional, programmamble strength internal pull-down/pull-up programmamble input/output line
bluegiga technologie s oy page 11 of 54 table 4 : terminal descriptions table 5 : terminal descriptions table 6 : terminal descriptions spi interface pin number pad type description pcm_out 36 output, tri-state, weak internal pull-down synchronous data output pcm_in 37 input, weak internal pull- down synchronous data input pcm_sync 34 bi-directional, weak internal pull-down synchronous data sync pcm_clk 35 bi-directional, weak internal pull-down synchronous data clock sdio/cspi/ua rt interfaces pin number pad type description sdio_data[0] synchronous data input/output cspi_miso cspi data output uart_tx uart data output, active high sdio_data[1] synchronous data input/output cspi_int cspi data input uart_rts# uart request to send output, active low sdio_data[2] synchronous data input/output uart_rx uart data input, active high sdio_data[3] synchronous data input/output cspi_cs# chip select for csr serial peripheral interface, active low uart_cts# uart clear to send input, active low sdio_clk sdio clock cspi_clk cspi clock sdio_sd_cs# 31 bi-directional, weak internal pull- down sdio chip select to allow sdio accessess sdio_cmd sdio data input cspi_mosi cspi data input 30 bi-directional, weak internal pull- 32 bi-directional, weak internal pull- 27 bi-directional, weak internal pull- 29 bi-directional, weak internal pull- down 25 bi-directional, tri- state, weak internal pull-down 26 bi-directional, weak internal pull- down spi interface pin number pad type description spi_mosi 41 weak internal pull-down spi data input spi_cs# 40 bi-directional, weak internal pull-down chip select for serial peripheral interface, active low spi_clk 39 bi-directional, weak internal pull-down spi clock spi_miso 38 output, tri-state, weak internal pull-down spi data output
bluegiga technologie s oy page 12 of 54 3 microcontroller, memory and baseband logic 3.1 auristream codec the auristream codec works o n the principle of transmitting the delta between the actual value of the signal and a prediction rather than the signal itself. hence, the information transmitted is reduced along with the power requirement. the quality of the output depends on the number of bits used to represent the sample. the inclusion of auristream results in reduced power consumption compared to a cvsd implementation when used at both ends of the system.
bluegiga technologie s oy page 13 of 54 3.1.1 auristream codec requirements auristream supports the following modes of operat ion: table 7 : auristream supported bitrates table key: = standard mode = optional mode where possible, auristream shares hardware between the encoder and decoder as well as the g726 and g722 implementations of the standard. the 40kbs and 20kbs modes of the g722 codec are specific to csr. the auristream module will be required to support the 3mbps stream transmitted by the bt radio. the worst - case scenario arises when the auristream block is configured as 16kbps at 8 khz, whi ch equates to 2 bits per sample, giving a worst - case symbol rate at the input to the auristream block of 1.5msps to sustain the transmitted bit stream. figure 2 : auristream codec and the bt radio 3.1.2 auristream hierarchy the auristr eam codec is positioned in parallel with the cvsd codec as shown in figure 4.
bluegiga technologie s oy page 14 of 54 figure 3 : auristream codec and the cvsd codec the auristream codec is controlled by the tx_rx_voicemain block and the processor. raw data from the host is read from the mmu by the transmit block. this data is fed via the tx_rx_voice_main module to the required codec, the encoded data is then fed back to the transmit block for broadcast over the bluetooth interface. during reception, the data is sourced f rom the radio and applied to the required codec. the decoded data is then stored back to ram by the bluetooth receiver. 3.2 memory managements unit the memory management unit (mmu) provides a number of dynamically allocated ring buffers that hold the data that is in transit between the host and the air. the dynamic allocation of memory ensures efficient use of the available random access memory(ram) and is performed by a hardware mmu to minimise the overheads on the processor during data/voice transfers. 3.3 burst mode controller during transmission the burst mode controller(bmc) constructs a packet from header information previously loaded into memory - mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the ram. during r eception, the bmc stores the packet header in memory - mapped registers and the payload data in the appropriate ring buffer in ram. this architecture minimises the intervention required by the processor during transmission and reception. 3.4 physical layer hardw are engine dsp dedicated logic is used to perform the following: ? forward error correction ? header error correction ? cyclic redundancy check ? encryption ? data whitening ? access code correlation ? audio transcoding
bluegiga technologie s oy page 15 of 54 the following voice data translations and operatio ns are performed by firmware: ? a - law/ - law/linear voice data (from host) ? a - law/ - law/continuously variable slope delta (cvsd) (over the air) ? voice interpolation for lost packets ? rate mismatches the hardware supports all optional and mandatory features of bl uetooth v2.1 + edr including afh and esco. 3.5 wlan coexistence dedicated hardware is provided to implement a variety of coexistence schemes. channel skipping afh, priority signalling, channel signalling and host passing of channel instructions are all support ed. the features are configured in firmware. for more information contact buegiga technical support. 3.6 configurable i/o parallel ports lines of programmable bi - directional input/outputs (i/o) are provided. pio[1: 5, 7, 9] are powered from vdd_pads. pio lines can be configured through software to have either weak or strong pull - ups or pull - downs. all pio lines are configured as inputs with weak pull - downs at reset. any of the pio lines can be configured as interrupt request lines or as wake - up lines from sleep modes. bluegiga cannot guarantee that the pio assignments remain as described. refer to the relevant software release note for the implementation of these pio lines, as they are firmware build - specific.
bluegiga technologie s oy page 16 of 54 4 clock generation wt21 uses an internal 26 mhz crys tal as a bluetooth reference clock. all wt21 internal digital clocks are generated using a phase locked loop, which is locked to the 26 mhz reference clock. also supplied to the digits is a watchdog clock, for use in low power modes. this uses a frequency of 32.768khz from clk_32k, or an internally generated reference clock frequency of 1khz, determined by pskey_deep_sleep_external_clock_source. the use of the watchdog clock is determined with respect to bluetooth operation in low power modes. figure 4 : clock architecture 4.1 32khz external reference clock a 32khz clock can be applied to clk_32k, using pskey_deep_sleep_external_clock_source. the clk_32k pad is in the vdd_pads domain with all the other digital i/o pads and is driven b etween levels specified in section 11.3.4. bluetooth radio digits pll 26 mhz 1 khz clk_32khz aio[0] watchdog clock
bluegiga technologie s oy page 17 of 54 5 serial peripheral interface (spi) 5.1 wt21 serial peripheral interface (spi) spi is used for debuging primarily. this section details the considerations required when interfacing to wt21 via the spi. data may be written or read one word at a time or the auto increment feature may be used to access blocks. 5.2 instruction cycle wt21 is the slave and receives commands on spi_mosi and outputs data on spi_miso. table 8 shows the instruction cycle for an spi transaction. table 8 : instruction cycle for an spi transaction with the exception of reset, spi_cs# must be held low during the transaction. data on spi_mosi is clocked into the wt21 on the rising edge of the clock line spi_clk. when reading, wt21 replies to the master on spi_miso with the data changing on the falling edge of the spi_clk. the master provides the clock on spi_clk. the transaction is terminated by taking spi_cs# high. sending a command word and the address of a register for every time it is to be read or written is a significant overhead, especially when large amounts of data are to be transferred. to overcome this wt21 offers increased data transfer efficiency via an auto increment operation. to invoke auto increment, spi_cs# is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or read. 5.2.1 writing to the device to write to wt21, the 8 - bit write command (00000010) is sent first (c[7:0]) followed by a 16 - bit address (a[15:0]). the next 16 - bits (d[15:0]) clocked in on spi_mosi are written to the location set by the address (a). thereafter for each subsequent 16 - bits clocked in, the address (a) is incremented and the data written to consecutive locations until the trans action terminates when spi_cs# is taken high.
bluegiga technologie s oy page 18 of 54 figure 5 : spi write operation 5.2.2 reading from the device reading from wt21 is similar to writing to it. an 8 - bit read command (00000011) is sent first (c [7:0]), followed by the address of the location to be read (a[15:0]). wt21 then outputs on spi_miso a check word during t[15:0] followed by the 16 - bit contents of the addressed location during bits d[15:0]. the check word is composed of {command, address [15:8]}. the check word may be us ed to confirm a read operation to a memory location. this overcomes the problems encountered with typical serial peripheral interface slaves, whereby it is impossible to determine whether the data returned by a read operation is valid data or the result of the slave device not responding. if spi_cs# is kept low, data from consecutive locations is read out on spi_miso for each subsequent 16 clocks, until the transaction terminates when spi_cs# is taken high. figure 6 : spi read oper ation 5.2.3 multi - slave operation wt21 should not be connected in a multi - slave arrangement by simple parallel connection of slave miso lines. when wt21 is deselected (spi_cs# = 1), the spi_miso line does not float. instead, wt21 outputs 0 if the processor is ru nning or 1 if it is stopped.
bluegiga technologie s oy page 19 of 54 6 host interfaces 6.1 host selection the mcu selects the uart/sdio interfaces by reading pio[4] at boot - time. when pio[4] is high, the sdio interface is enabled; when pio[4] is low, the uart is enabled. if in uart mode, the mcu sele cts the uart transfer protocol automatically using the unused sdio pins shown in table 9 table 9 : sdio_clk and sdio_cmd transfer protocols 6.2 uart interface this is a standard uart interface for communicatin g with other serial devices. wt21 uart interface provides a simple mechanism for communicating with other serial devices using the rs232 protocol. note: wt21 uses rs232 protocol, but voltage levels are 0v to vdd_pads (requires external rs232 transceiver c hip. figure 7 : universal asynchronous receiver four signals implement the uart function, as shown in figure 8. when wt21 is connected to another digital device, uart_rx and uart_tx transfer data between the two devices. the remai ning two signals, uart_cts and uart_rts, can be used to implement rs232 hardware flow control where both are active low indicators. sdio_clk sdio_cmd protocol 0 0 bcsp 0 1 h4 1 0 h4ds 1 1 h5 uart_tx uart_rx uart_rts# uart_cts#
bluegiga technologie s oy page 20 of 54 uart configuration parameters, such as baud rate and packet format, are set using wt21 firmware. note: an accelerated serial port adapter is required to communicate with the uart at maximum baud rate using a standard pc. table 10 : possible uart settings note: baud rate is the measure of symbol rate i.e. , the number of distinct symbol changes (signalin g events) made to transmission medium per second in a digitally modulated signal. the uart interface is capable of resetting wt21 on reception of a break signal. a break is identified by a continuous logic low (0v) on the uart_rx terminal, as shown in figu re 9. if tbrkis longer than the value, defined by the pskey_hostio_uart_reset_timeout, (0x1a4), a reset occurs. this feature allows a host to initialise the system to a known state. also, wt21 can emit a break character that may be used to wake the host. b y default this feature is disabled and it is recommended to enable it by setting pskey_hostio_uart_reset_timeout. figure 8 : break signal table 11 shows a list of commonly used baud rates and their associated values for the pskey_ uart_baudrate (0x1be). there is no requirement to use these standard values. any baud rate within the supported range can be set in the ps key according to the formula in equation xxx. equation 1 : baud rate
bluegiga technologie s oy page 21 of 54 table 11 : standard baud rates 6.2.1 uart configuration while reset is active the uart interface for wt21 is tri - state while the chip is being held in reset. this allows the user to daisy chain devices onto the physical uart bus. the constraint on this meth od is that any devices connected to this bus must tri - state when wt21 reset is de - asserted and the firmware begins to run.
bluegiga technologie s oy page 22 of 54 7 csr serial peripheral interface (cspi) the cspi is a host interface which shares pins with the sdio. it has been defined by csr with the intention of producing a very simple interface. this has two advantages: ? it allows maximum compatibility with the possible host drivers ? it minimizes the host software effort needed to form that data to be sent (e.g., by removing the need to calculate crcs) this host interface allows an external host to control the bluecore, using a csr defined protocol built upon a 4 - wire spi bus. note: the cspi is entirely separated from the debug serial peripheral interface the cspi allows access to the following: ? fu nction 0 registers ? bluetooth acceleration registers ? mcu io registers ? bluetooth mmu port the cspi is a third protocol available for the host to transfer data into the bluecore and shares pins with the other sdio protocols. mmu buffers are accessed using bur st read/writes. the command and address fields are used to select the correct buffer. the cspi is able to generate an interrupt to the host when a memory access fails. this interrupt line is shared with the sdio functions. table 12 shows the mapping of sdi o pins onto the cspi functions when cspi is enabled. table 12 : sdio mapping to cspi functions the cspi interface is an extension of the basic spi interface, with the access type determined by the following fields: ? 8 - bit command ? 24 - bit address ? 16 - bit burst length (optional). only applicable for burst transfers into or out of the mmu 7.1.1 cspi read/write cycles register read/write cycles are used to access function 0, bluetooth acceleration and mcu registers. burst read/write cycles are u sed to access the mmu.
bluegiga technologie s oy page 23 of 54 7.1.2 cspi register write cycle the command and address are locked into the slave, followed by 16bits of write data. an error byte is returned on the miso signal indicating whether or not the transfer has been successful. figure 9 : cspi register write cycle 7.1.3 cspi register read cycle the command and address field are clocked into the slave, the slave then returns the following: ? bytes of badding data (miso held low) ? error byte ? 16 - bits of read data figure 10 : cspi register read cycle 7.1.4 cspi register burst write cycle burst transfers are used to access the mmu buffers. they cannot be used to access registers. burst read/write cycles are selected by setting the nregister/burst bit in the command field to 1. burst transfers are byte orientated, have a minimum length of 0 bytes and a maximum length of 64kbytes. setting the length field to 0 results in no data being transferred to or from the mmu. as with a register access, the command and address fi elds are transferred first. there is an optional length field transferred after the address. the use of the length field is controlled by the lengthfieldpresent bit in the function 0 registers, which is cleared on reset. figure 11 : cspi burst write cycle
bluegiga technologie s oy page 24 of 54 7.1.5 cspi register read cycle burst reads have a programmable amount of padding data that is returned by the slave. 0 - 15 bytes are returned as defined in the burstpadding register. following this the error byte is returned followed by the data. once the transfer has started, no further padding is needed. a fifo within sdio_top will pre - fetch the data. the address is not retransmitted, and is auto - updated within the slave. the length field is transmitted if lengthfieldpresentin the funct ion 0 registers is set. in the absence of a length field the csb signal is used to indicate the end of the burst. figure 12 : cspi burst read cycle
bluegiga technologie s oy page 25 of 54 7.2 sdio interface this is a host interface which allows a secure digital input outp ut(sdio) host to gain access to the internals of the chip. it provides all defined slave modes (spi, sd 1bit, sd 4bit), but not sd host function. the function provided includes generating responses to each command in hardware and implementing the state mac hines defined in the sdio specification. within the various modes of operation, it provides initialisation functions (cmds 0, 3, 5, 7, 15, 59) and two other functions: ? function 1 provides bluetooth type a support, and follows that specification ? function 2 provides generic register access(cmd52 (byte read/write)) for more information, see the following specifications: ? sd specifications part 1 physical layer specification v.1.10 ? sd specification part e1 sdio specification v.1.10 ? sdio card part e2 type - a speci fication for bluetooth v.1.00 7.2.1 sdio/cspi deep - sleep control schemes this is the lowest power mode, where the processor, the internal reference (fast) clock, and much of the digital and analogue hardware are shut down. to support this power consumption reduc tion solution and to prevent any errors arising on the sdio host interface there are two deep - sleep control schemes. ? scheme 1: the host retransmits any packets that bluecore was unable to receive as a result of being in deep - sleep ? scheme 2: introduces addi tional signaling to prevent the need for retransmissions during deep - sleep the internal reference clock is turned off. however, the host transport protocols (sd/uart/cspi) are driven from the sdio clock and so continue to function during deep - sleep, enabli ng access to the function 0 interface, but not the function 1 interface. 7.2.2 retransmission bluecore enters deep - sleep whenever it becomes idle after which time, when the host transmits a message on function 1 an illegal command error will be signaled. the act ivity that this initiates on the sdio interface provokes bluecore into wakeup after which the host re - transmits the original message. bluecore will wait for a configurable period of time before re - entering deep - sleep, thus ensuring that the original packet is sent/received on retransmission. this control scheme is the default mode of operation. 7.2.3 signaling signalling between the host and bluecore enables host control over bluecore deep - sleep mode. consequently the host is aware of when it is appropriate to se nd bluecore hci traffic over function 1. the signals used by this scheme are host wakeup and ready status interrupt select, implemented as register bit in the vendor unique area of function 0.
bluegiga technologie s oy page 26 of 54 8 audio interfaces 8.1 pcm interface the audio pulse code modulation (pcm) interface supports continuous transmission and reception of pcm encoded audio data over bluetooth. pulse code modulation (pcm) is a standard method used to digitise audio (particularly voice) for transmission over digital communication channels. thro ugh its pcm interface, wt21 has hardware support for continual transmission and reception of pcm data, thus reducing processor overhead for wireless headset applications. bluecore6 - rom (qfn) offers a bi - directional digital audio interface that routes direc tly into the baseband layer of the on - chip firmware. it does not pass through the hci protocol layer. hardware on wt21 allows the data to be sent to and received from a sco connection. up to three sco connections can be supported by the pcm interface at an y one time. wt21 can operate as the pcm interface master generating an output clock of 128, 256, 512, 1536 or 2400khz. when configured as a pcm interface slave, it can operate with an input clock up to 2400khz. wt21 is compatible with a variety of clock fo rmats, including long frame sync, short frame sync and gci timing environments. it supports 13 - bit or 16 - bit linear, 8 - bit - law or a - law companded sample formats at 8ksamples/s and can receive and transmit on any selection of three of the first four slots following pcm_sync. the pcm configuration options are enabled by setting the pskey_pcm_config32 (0x1b3). wt21 interfaces directly to pcm audio devices including the following: 8.1.1 pcm interface master/slave when configured as the master of the pcm interface , bluecore6 - rom (qfn) generates pcm_clk and pcm_sync.
bluegiga technologie s oy page 27 of 54 figure 13 : wt21 as a pcm interface master figure 14 : wt21 as a pcm interface slave 8.1.2 long frame sync long frame sync is the name given to a clocking format that controls the transfer of pcm data words or samples. in long frame sync, the rising edge of pcm_sync indicates the start of the pcm word. when wt21 is configured as pcm master, generating pcm_sync and pcm_clk, then pcm_sync is 8 - bits long. when wt21 is configured as pcm slave, pcm_sync may be from two consecutive falling edges of pcm_clk to half the pcm_sync rate, i.e., 62.5 s long.
bluegiga technologie s oy page 28 of 54 figure 15 : long frame sync (shown with 8 - bit companded sample) bluecore6 - rom (qfn) samples pcm_in on the falling edge of pcm_clk and transmits pcm_out on the rising edge. pcm_out may be configured to be high impedance on the falling edge of pcm_clk in the lsb position or on the rising edge. 8.1.3 short frame sync in short frame sync, the falling edge of pcm_sync indicates the start of the pcm word. pcm_sync is always one clock cycle long. figure 16 : s hort frame sync (shown with 16 - bit sample) as with long frame sync, bluecore6 - rom (qfn) samples pcm_in on the falling edge of pcm_clk and transmits pcm_out on the rising edge. pcm_out may be configured to be high impedance on the falling edge of pcm_clk in the lsb position or on the rising edge. 8.1.4 multi - slot operation more than one sco connection over the pcm interface is supported using multiple slots. up to three sco connections can be carried over any of the first four slots.
bluegiga technologie s oy page 29 of 54 figure 17 : multi - slot operation with two slots and 8 - bit companded samples 8.1.5 gci interface wt21 is compatible with the general circuit interface (gci), a standard synchronous 2b+d isdn timing interface. the two 64kbps b channels can be accessed when this mode i s configured. figure 18 : gci interface the start of frame is indicated by the rising edge of pcm_sync and runs at 8khz. with wt21 in slave mode, the frequency of pcm_clk can be up to 4.096mhz. 8.1.6 slots and sample formats wt21 can re ceive and transmit on any selection of the first four slots following each sync pulse. slot durations can be either 8 or 16 clock cycles. durations of 8 clock cycles may only be used with 8 - bit sample formats. durations of 16 clocks may be used with 8 - bit, 13 - bit or 16 - bit sample formats. wt21 supports 13 - bit linear, 16 - bit linear and 8 - bit - law or a - law sample formats. the sample rate is 8ksamples/s. the bit order may be little or big endian. when 16 - bit slots are used, the 3 or 8 unused bits in each slot may be filled with sign extension, padded with zeros or a programmable 3 - bit audio attenuation compatible with some motorola codecs.
bluegiga technologie s oy page 30 of 54 figure 19 : 16 - bit slot length and sample formats 8.1.7 additional features wt21 has a mute facility t hat forces pcm_out to be 0. in master mode, pcm_sync may also be forced to 0 while keeping pcm_clk running which some codecs use to control power down.
bluegiga technologie s oy page 31 of 54 8.1.8 pcm timing information figure 20 : pcm master timing a) assumes normal system c lock operation. figures will vary during low power modes, when system clock speeds are reduced.
bluegiga technologie s oy page 32 of 54 figure 21 : pcm master timing long frame sync figure 22 : pcm master timing short frame sync
bluegiga technologie s oy page 33 of 54 table 13 : pcm slave timing figure 23 : pcm slave timing long frame sync
bluegiga technologie s oy page 34 of 54 figure 24 : pcm slave timing short frame sync 8.1.9 pcm_clk and pcm_sync generation wt21 has two methods of generating pcm_clk and pcm_sync in master mode. the first is generating these signals by direct digital synthesis(dds) from wt21 internal 4mhz clock. using this mode limits pcm_clk to 128, 256 or 512khz and pcm_sync to 8khz. the second is generating pcm_clk and pcm_sync by d ds from an internal 48mhz clock (which allows a greater range of frequencies to be generated with low jitter but consumes more power). this second method is selected by setting bit 48m_pcm_clk_gen_en in pskey_pcm_config32. when in this mode and with long f rame sync, the length of pcm_sync can be either 8 or 16 cycles of pcm_clk, determined by long_length_sync_en in pskey_pcm_config32. equation xxx describes pcm_clk frequency when being generated using the internal 48mhz clock: equation 2 : pcm_sync frequency relative to pcm_clk cnt_rate, cnt_limit and sync_limit are set using pskey_pcm_low_jitter_config. as an example, to generate pcm_clk at 512khz with pcm_sync at 8khz, set pskey_pcm_low_jitter_config to 0x08080177. 8.1.10 pcm configura tion the pcm configuration is set using the ps keys, pskey_pcm_config32 described in table 14, pskey_pcm_low_jitter_config in table 13, and pskey_pcm_sync_mult in table 15. the default for pskey_pcm_config32is 0x00800000, i.e., first slot following sync is active, 13 - bit linear voice format, long frame sync and interface master generating 256khz pcm_clk from 4mhz internal clock with no tri - state of pcm_out.
bluegiga technologie s oy page 35 of 54 table 14 : pskey_pcm_low_jitter_config description
bluegiga technologie s oy page 36 of 54 table 15 : pskey_pcm_config32 description
bluegiga technologie s oy page 37 of 54 table 16 : pskey_pcm_sync_mult description 8.2 digital audio interface (i2s) the digital audio interface supports the industry standard formats for i2s, left - justified (lj) or right - justified(r j). the interface shares the same pins as the pcm interface, which means each audio bus is mutually exclusive in its usage. table 17 lists these alternative functions. figure 26 shows the timing diagram. table 17 : alternative func tions of the digital audio bus interface on the pcm interface. table 18 describes the values for the ps key (pskey_digital_audio_config) that is used to set - up the digital audio interface. for example, to configure an i2s interface with 16 - bit sd data set pskey_digital_config to 0x0406. table 18 : pskey_digital_audio_config
bluegiga technologie s oy page 38 of 54 figure 25 : digital audio interface modes the internal representation of audio samples within bluecore6 - rom (qfn) is 16 - bit and data on sd_out is limited to 16 - bit per channel. table 19 : digital audio interface slave timing
bluegiga technologie s oy page 39 of 54 figure 26 : digital audio interface slave timing table 20 : digital audio interface master timing figure 27 : digital audio interface master timing
bluegiga technologie s oy page 40 of 54 9 power control and regulation 9.1 power control and regulation wt21 contains two linear regulators. ? a high voltage regulator to generate 1,8 v rail for the module i/os ? a low vo ltage regulator to supply the 1,5 v core from the 1,8 v rail the module can be powered from a high - voltage rail through both regulators and the output of the high - voltage regulator can be used as a supply voltage for the digital interfaces of the module (v dd_pads). alternatively vdd_pads can be supplied by an external voltage source and 1v8 regulator can be by - passed by connecting 1.8 v from an external regulator directly to 1v8_out . if the i/o supply vdd_pads is powered before the 1.5v supplies the digital pads default to their no core voltage reset state. figure 28 : voltage regulator configuration 9.2 vreg_enable the regulator enable pin vregenable is used to enable the wt21. vregenable enables both the high voltage regulator and the low voltage regulator. the pin is active high, with a logic threshold of around 1v, and has a weak pull - down. vregenable can tolerate voltages up to 4.9v, so may be connected directly to a battery to enable the device. 9.3 rst# wt21 may be reset from several sources: rst# pin, power on reset, a uart break character or via a software configured watchdog timer. the rst# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. a reset is performed between 1.5 and 4. 0ms following rst# being active. it is recommended that rst# be applied for a period greater than 5ms. the power on reset occurs when the core supply falls below typically 1.24v and is released when core voltage rises above typically 1.31v. at reset the di gital i/o pins are set to inputs for bi - directional pins and outputs are tri - state. the pull - down state is shown in table 21. following a reset, wt21 assumes the maximum xtal frequency, which ensures that the internal clocks run at a safe (low) frequency u ntil wt21 is configured for the actual xtal frequency. 1v8_out vregin vreg_ena 1v8 linear regulator 1v5 linear regulator rf circuitry vdd_pads digital circuitry and interfaces
bluegiga technologie s oy page 41 of 54 9.4 digital pin states on reset the digital i/o interfaces on the wt21 device are optimised for minimum power consumption after initialisation of digital interfaces. table 21 shows the pin states of wt21 on reset. pull - up (pu) and pull - down (pd) default to weak values unless specified otherwise.
bluegiga technologie s oy page 42 of 54 table 21 : pin states of wt21 on reset pull r i/o pull r i/o rst# digital input pu input pu input pull r i/o pull r i/o sdio_data[3] digital bi-directional pd input pu input sdio_data[2] digital bi-directional pd input pu input sdio_data[1] digital bi-directional pd input pu input sdio_data[0] digital bi-directional pd input pu input sdio_sd_cs# digital bi-directional pd input pu input sdio_cmd digital bi-directional pd input pu input sdio_clk digital bi-directional pd input pu input pull r i/o pull r i/o pcm_in digital input pd input pd input pcm_out digital tri-state output pd high impedance pd high impedance pcm_clk digital bidirectional pd input pd input pcm_sync digital bidirectional pd input pd input pull r i/o pull r i/o spi_mosi digital input pd input pd input spi_clk digital input pd input pd input spi_cs# digital input pu pu pu input spi_miso digital tri-state output pd pd pd high impedance pull r i/o pull r i/o pio[0] digital bi-directional pd input pd input pio[1] digital bi-directional pd input pd input pio[2] digital bi-directional pd input pd input pio[3] digital bi-directional pd input pd input pio[4] digital bi-directional pd input pd input pio[5] digital bi-directional pd input pd input pio[7] digital bi-directional pd input pd input pio[9] digital bi-directional pd input pd input pull r i/o pull r i/o clk_32k digital input pd input pd input pios spi interface pin name / group i/o type no core voltage reset full chip reset pin name / group i/o type no core voltage reset full chip reset pin name / group i/o type no core voltage reset full chip reset reset / control pin name / group i/o type full chip reset pcm interface digital interfaces - sdio no core voltage reset pin name / group i/o type no core voltage reset full chip reset clock pin name / group i/o type no core voltage reset full chip reset
bluegiga technologie s oy page 43 of 54 10 bluetooth radio 10.1 bluetooth receiver the receiver features a near - zero inte rmediate frequency (if) architecture that allows the channel filters to be integrated onto the die. sufficient out - of - band blocking specification at the low noise amplifier (lna) input allows the receiver to be used in close proximity to global system for mobile communications(gsm) and wideband code division multiple access (w - cdma) cellular phone transmitters without being desensitised. the use of a digital frequency shift keying(fsk) discriminator means that no discriminator tank is needed and its excelle nt performance in the presence of noise allows wt21 to exceed the bluetooth requirements for co - channel and adjacent channel rejection. for edr, the demodulator contains an adc which is used to digitise the if received signal. this information is then pass ed to the edr modem. 10.1.1 rssi analogue to digital converter the analogue to digital converter (adc) implements fast automatic gain control (agc). the adc samples the received signal strength indicator (rssi) voltage on a slot - by - slot basis. the front - end lna g ain is changed according to the measured rssi value, keeping the first mixer input signal within a limited range. this improves the dynamic range of the receiver, improving performance in interference limited environments. 10.2 bluetooth transmitter the transmi tter features a direct iq modulator to minimise the frequency drift during a transmit timeslot, which results in a controlled modulation index. digital baseband transmit circuitry provides the required spectral shaping. the internal power amplifier (pa) ha s a maximum output power of +6dbm.
bluegiga technologie s oy page 44 of 54 11 electrical characteristics 11.1 absolute maximum ratings table 22 : absolute maximum ratings 11.2 recommended operating conditions table 23 : r e commended operating conditions 11.3 input/output terminal characteristics 11.3.1 linear voltage regulator table 24 : recommende d operating conditions min max unit -40 85 c io voltage vdd_pads -0.4 3.7 v supply voltage vreg_in, vreg_ena -0.4 4.9 v vss-0.4 vdd+0.4 v rating storage temperature other terminal voltages min max unit tbd tbd c io voltage vdd_pads 1.7 3.7 v rating operating temperature range normal operation min typ max unit input voltage 2.7 - 4.9 v output voltage (i load = 70 ma / vreg_in = 3.0 v) 1.7 1.8 1.9 v temperature coefficient -250 0 250 ppm/c output noise - - 1 mv rms load regulation (i load < 70 ma) - - 50 mv/a settling time - - 50 s maximum output current 70 - - ma minimum load current 5 - - a drop-out voltage (i load = 70 ma) - - 600 mv quiescent current (excluding load, i load < 100 a) 30 40 60 a low power mode quiescent current (excluding load, i load < 100 a) 10 13 21 a standby mode quiescent current (excluding load, i load < 100 a) 1.5 2.5 3.3 a
bluegiga technologie s oy page 45 of 54 11.3.2 digital table 25 : digital terminal electrical characteristics 11.3.3 reset table 26 : power on reset characteristics 11.3.4 32 khz external reference clock table 27 : external reference clock digital terminals min typ max unit v il input logic level low 1.7v vdd 3.6v -0.4 - 0.25xvdd v v ih input logic level high 1.7v vdd 3.6v 0.7vdd - vdd+0.3 v v ol output logic level low 1.7v vdd 3.6v, (i o = 4.0 ma) - - 0.125 v v oh output logic level high 1.7v vdd 3.6v, (i o = -4.0 ma) vdd-0.4 - vdd v strong pull-up -100 -40 -10 a strong pull-down 10 40 100 a weak pull-up -5 -1 -0.2 a weak pull-down 0.2 1 5 a i/o pad leakage curren -1 0 1 a cl input capacitance 1 - 5 pf input voltage levels output voltage levels input tri-state current with: power-on reset min typ max unit vdd_core (a falling threshold 1.13 1.24 1.3 v vdd_core (a rising threshold 1.2 1.31 1.35 v hysteresis 0.05 0.07 0.15 v (a vdd_core is a core voltage supplied by the internal 1.5 v voltage regulator. min nom max frequency 32748 32768 32788 hz frequency deviation @25c - - 20 +/- ppm frequency deviation -25c to 85c - - 150 +/- ppm input high level square wave 0.625xvdd_pads - - v input low level square wave - - 0.425xvdd_pads v duty cycle square wave 30 - 70 % rise and fall time - - 50 ns integrated frequency jitter integrated over the band 200 hz to 15 khz - - - hz (rms) units parameter conditions/not es specifications
bluegiga technologie s oy page 46 of 54 11.4 power consumption table 28 : power consumption operation mode connection type average unit page scan, time interval 1.28s - 0.4 ma inquiry and page scan, time interval1,28s - 0.8 ma acl no trafic master 4 ma acl with file transfer master 9 ma acl 40ms sniff master 2 ma acl 1,28s sniff master 0.2 ma esco ev5 master 12 ma esco ev3 master 18 ma esco ev3 - hands-free - setting s1 master 18.5 ma sco hv1 master 37 ma sco hv3 master 17 ma sco hv3 30ms sniff master 17 ma acl no traffic slave 14 ma acl with file transfer slave 17 ma acl 40ms sniff slave 1.6 ma acl 1.28s sniff slave 0.2 ma esco ev5 slave 19 ma esco ev3 slave 23 ma esco ev3 - hands-free - setting s1 slave 23 ma sco hv1 slave 37 ma sco hv3 slave 23 ma sco hv3 30ms sniff slave 16 ma standby host connection (deep-sleep) - 40 a reset (active low) - 39 a note: conditions 20c vreg_in 3.15v vdd_pads 3.15v uart baud rate 115.2 kbps
bluegiga technologie s oy page 47 of 54 12 physical dimensions figure 29 : physical dimensions figure 30 : wt21 - a recomme nded pcb land p atte r n
bluegiga technologie s oy page 48 of 54 figure 31 : wt21 - n recommended pcb land pattern
bluegiga technologie s oy page 49 of 54 figure 32 : detailed dimensions 2.5 mm 9.7 mm 17.1 mm 6.8 mm 2.2 mm 17.1 mm 9.7 mm 10.4 mm 11.6 mm
bluegiga technologie s oy page 50 of 54 13 layout guidelines 13.1 wt21 - n rf output can be taken directly from the rf test point (rftp) of the modu le. rftp has a signal pin surrounded by a ground. dimensions for the rftp are shown in the figure below. use 50 ohm trace to route rf from rftp. with wt21 - a leave rftp floating and do not place copper directly under rftp. figure 33 : dimensions of the rftp 13.2 wt21 - a figure 34 : example layout
bluegiga technologie s oy page 51 of 54 do not connect rftp for wt21 - a. see figure 32 for the recommended pcb land patern. the impedance matching of the antenna is design for the evaluation board of wt21. for an optimal performance of the antenna the layout should strictly follow the layout example shown in figure 31 and the thickness of fr4 should be 1,6 mm. any dielectric material close to the antenna will change the resonant frequency and it is recommen ded not to place a plastic case or any other dielectric closer than 5 mm from the antenna. if this is not possible, or if using other thickness of fr4 than 1,6 mm, then the antenna can be retuned by removing extra fr4 under the antenna. please, contact blu egiga for the details. any metal in close proximity of the antenna will prevent the antenna to radiate freely. it is recommended not to place any metal closer than 20 mm from the antenna. following recommendations helps to avoid emc problems arising in th e design. note that each design is unique and the following list do not consider all basic design rules such as avoiding capacitive coupling between signal lines. following list is aimed to avoid emc problems caused by rf part of the module. ? do not remove copper from the pcb more than needed. use ground filling as much as possible. however remove small floating islands after copper pour. ? do not place a ground plane underneath the antenna. the grounding areas under the module should be designed as shown in figure 31. ? when using overlapping ground areas use conductive vias separated max. 3 mm apart at the edge of the ground areas. this prevents rf to penetrate inside the pcb. use ground vias extensively all over the pcb. all the traces in (and on) the pcb are potential antennas. ? avoid loops. ? ensure that signal lines have return paths as short as possible. with sensitive analog signals, such as analog audio, use solid ground plane and make sure that the return path for the signal lines is low impedance and foll ows the signal lines all the way.
bluegiga technologie s oy page 52 of 54 14 certifications wt21 is compliant to the following specifications. 14.1 bluetooth wt21 module is bluetooth qualified a nd listed as a controller subsystem and it is bluetooth compliant to the following profiles of the core spec version 2.1/2.1+edr . rf, baseband, link manager, host controller interface, serial port profile and rfcomm with ts 07.10. bluetooth qdid: b016019 14.2 fcc this device complies with part 15 of the fcc rules. operation is subject to the following two co ndi tions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. fcc rf radiation exposure statement: this equipment complies with fcc radia tion exposure limits set forth for an uncontrolled environment. end users must follow the specific operating instructions for satisfying rf exposure compliance. this transmitter must not be co - located or operating in conjunction with any other antenna or t ransmitter. note: when using wt21 - a t he end product must display an exterior label with the following detail incorporated: contains trans mitter module fcc id: qoqwt21a when using wt21 - n t he end product must display an exterior label with the following detail incorporated: contains trans mitter module fcc id: qoqwt21n
bluegiga technologie s oy page 53 of 54 14.3 ce wt21 meets the requirements of the standards below and hence fulfills the requirements of emc directive 89/336/eec as amended by directives 92/31/eec and 93/68/eec within ce marking requirement. ? emc (immunity only ) en 301 489 - 17 v.1.3.3 in accordance with en 301 489 - 1 v1.8.1 ? radiated emissions en 300 328 v1.7.1 14.4 industry canada (ic) wt 21 - a and wt21 - n meets industry canadas procedural and specification requirements for certification . i ndustry canada id: 5123a - bgtwt21a industry canada id: 5123a - bgtwt21n 14.5 qualified antenna types for wt21 - n this device has been designed to operate with the antennas listed belo w, and having a maximum gain of 2 db. antennas not included in this list or havin g a gain greater than 2 db are strictly prohibited for use with this device. th e required antenna impedance is 50 ohms. table 29 : qualified antenna types for wt21 - n any antenna that is of the same type a nd of equal or less directional gain as listed in table 29 can be used without a need for retesting. to reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power ( e.i.r.p.) is not more than that permitted for successful communication. using an antenna of a different type or gain more than 2 dbi will require additional testing for fcc, ce and ic. please, contact support@blu egiga.com for more information. antenna type maximum gain dipole 2 dbi qualified antenna types for wt21-n
bluegiga technologie s oy page 54 of 54 15 contact i nformation sales: sales@bluegiga.com technical support: support@bluegiga.com http://www.bluegiga.com/techforum/ orders : orders@bluegiga.com head office / finland : phone: +358 - 9 - 4355 060 fax: +358 - 9 - 4355 0660 street address: sinikalliontie 5a 02630 espoo finland postal address: p.o. box 120 02631 espoo finland sales office / usa : phone: (781) 556 - 1039 bluegiga technologies, inc. 99 derby street, suite 200 hingham, ma 02043

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